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mipi/dsi receiver with hdmi transmitter adv7533 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features general low power mipi/dsi receiver low power hdmi/dvi transmitter ideal for portable applications cec controller and expanded message buffer (3 messages) reduces system overhead incorporates hdmi v.1.3 (x.v.color?) technology compatible with dvi v.1.0 optional embedded hdcp keys to support hdcp 1.3 1.8 v, 1.2 v (optional), and 3.3 v supplies for ultralow operating power audio inputs accept logic levels from 1.8 v to 3.3 v mipi/dsi receiver 2-, 3-, or 4-lane dsi receiver supports up to 800 mbps per lane compatible with dphy v.0.90 and dsi v.1.02 supports inputs of 16-bit rgb 4:4:4 24-bit rgb 4:4:4 30-bit rgb 4:4:4 hdmi (tmds) video out 80 mhz operation supports all video and graphics resolutions from 480i to 1080p at 30 hz programmable 2-way color space converter output supports 36-, 30-, or 24-bit rgb 4:4:4 36-, 30-, or 24-bit ycbcr 4:4:4 automatic input video format timing detection (cea-861e) digital audio supports standard s/pdif for stereo lpcm or compressed audio up to 192 khz 2-channel uncompressed lpcm i 2 s audio up to 192 khz special features for easy system design on-chip mpu with i 2 c master to perform edid reading and hdcp operations; reports hdmi events through interrupts and registers 5 v tolerant i 2 c and hpd i/os, no extra device needed no audio master clock needed for supporting s/pdif and i 2 s applications mobile systems cellular handsets digital video cameras digital still cameras personal media players gaming general description the adv7533 is a multifunction video interface chip. the adv7533 provides a mobile industry processor interface/ display serial interface (mipi?/dsi) input port, a high definition multimedia interface (hdmi?) data output in a 49-ball wafer level chip scale package (wlcsp). the display serial interface (dsi) input provides up to four lanes of mipi/dsi data, each running up to 800 mbps. the dsi rx implements dsi video mode operation only. the hdmi tx supports video resolutions using pixel clocks of up to 80 mhz. with the optional inclusion of embedded hdcp keys, the adv7533 allows the secure transmission of protected content, as specified by the hdcp 1.3 protocol. the adv7533 supports x.v.color? (gamut metadata) for a wider color gamut. the adv7533 supports both s/pdif and 2-channel i 2 s audio. its high fidelity 2-channel i 2 s can transmit stereo up to a 192 khz sampling rate. the s/pdif can carry stereo lpcm audio or compressed audio, including dolby? digital and dts?. the adv7533 helps to reduce system design complexity and cost by incorporating such features as an i 2 c master for edid reading and 5 v tolerance on the i 2 c and hot plug? detect pins. fabricated in an advanced cmos process, the adv7533 is available in a space saving, 49-ball, wlcsp surface mount package. this package is rohs compliant and specified to operate from ?10c to +85c.
adv7533 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? specifications..................................................................................... 4 ? mipi/dsi specifications.............................................................. 6 ? absolute maximum ratings............................................................ 8 ? esd caution...................................................................................8 ? explanation of test levels............................................................8 ? pin configuration and function descriptions..............................9 ? applications information .............................................................. 11 ? design resources ....................................................................... 11 ? outline dimensions ....................................................................... 12 ? ordering guide .......................................................................... 12 ? revision history 7/11revision 0: initial version
adv7533 rev. 0 | page 3 of 12 functional block diagram audio data capture cec controller buffer hdcp encryption hdcp keys n/v memory cec_clk cec spdif/i2s lrclk sclk/mcl k hdcp and edid micro- controller ddc_scl ddc_sda sda scl hpd int ctrl adv7533 sync adjust and generation drx0 drx1 drxc drx2 2 2 2 2 hdmi_tx0 hdmi_tx1 hdmi_tx2 hdmi_txc hdmi tmds tx dsi decode power avdd dvdd a2vdd v1p2 gnd v3p3 pd color space converter r_ext pvdd drx3 2 2 2 2 2 up/ down dither pattern generator band gap i 2 c slave i 2 c master 4 ch dphy 09821-001 figure 1.
adv7533 rev. 0 | page 4 of 12 specifications table 1. electrical specifications adv7533bcbz parameter conditions temp test level 1 min typ max unit digital inputs data inputsaudio, cec_clk input voltage, high (v ih ) full vi 1.4 3.5 v input voltage, low (v il ) full vi ?0.3 +0.7 v input capacitance 25c viii 1.0 1.5 pf i 2 c lines (sda, scl) input voltage, high (v ih ) full vi 1.3 5.5 v input voltage, low (v il ) full vi ?0.3 +0.6 v i 2 c lines (ddcsda, ddcscl) input voltage, high (v ih ) default values full vi 1.3 5.5 v input voltage, low (v il ) full vi ?0.3 +0.6 v input voltage, high (v ih ) programmable optional values full iv 3.5 5.5 v input voltage, low (v il ) full iv ?0.5 +1.2 v cec input voltage, high (v ih ) full vi 2.0 v input voltage, low (v il ) full vi 0.6 v output voltage, high (v oh ) full vi 2.5 3.63 v output voltage, low (v ol ) full vi ?0.3 +0.6 v hpd input voltage, high (v ih ) full vi 1.3 5.5 v input voltage, low (v il ) full vi ?0.3 +0.6 v digital outputsint output voltage, low (v ol ) load = 5 pf full vi 0.4 v thermal characteristics thermal resistance jc junction-to-case full v 20 c/w ja junction-to-ambient full v 43 c/w ambient temperature full v ?10 +25 +85 c dc specifications input leakage current, i il 25c vi ?1 +1 a power supply 1.8 v supply voltage (dv dd , av dd , a2v dd , pv dd ) full iv 1.71 1.8 1.9 v v1p2 = (1.2 v) full iv 1.14 1.2 1.26 v v1p2 = (1.8 v) full iv 1.71 1.8 1.9 v supply voltage noise limit dvdd digital i/o pad logic full iv 64 mv rms avddhdmi analog core full iv 64 mv rms v1p2hdmi/dsi digital core 1.2 v full iv 43 mv rms 1.8 v full iv 64 mv rms a2vddmipi dphy full iv 64 mv rms pvddhdmi pll refer to figure 2 full iv mv rms 3.3 v supply voltage (v3p3) full iv 3.15 3.30 3.45 v 3.3 v supply voltage noise limit full iv 64 mv rms power-down current 25c vi 15 a operating current dvdd i/o pads (30 bits at 720p) full iv 6 ma
adv7533 rev. 0 | page 5 of 12 adv7533bcbz parameter conditions temp test level 1 min typ max unit avdd hdmi analog core (24 bits at 720p) full iv 11 ma v1p2 (1.2 v) hdmi/dsi digital core (dsi 30 bits/hdmi 24 bits at 720p) full iv 39 ma a2vdd mipi dphy (30 bits/three lanes/720p) full iv 12 ma pvdd hdmi pll (24 bits at 720p) full iv 11 ma v3p3hdmi/hdcp memory hdmi hdcp memory full iv 0.3 ma transmitter total power 720p, 30-bit dsi in; 720p, 36-bit hdmi out; typical random pattern with csc enabled, hdcp enabled, audio enabled v1p2 = 1.2 v full iv 120 154 mw v1p2 = 1.8 v full vi 204 mw ac specifications tmds output clock frequency 25c iv 20 112 mhz tmds output clock duty cycle 25c iv 48 52 % tmds differential swing 25c vii 800 1000 1200 mv differential output timing low-to-high transition time 25c vii 75 175 ps high-to-low transition time 25c vii 75 175 ps audio ac timing 2 sclk duty cycle when n = even number full iv 40 50 60 % when n = odd number full iv 49 50 51 % i 2 s, s/pdif setup, t asu full iv 2 ns i 2 s, s/pdif hold time, t ahld full iv 2 ns lrclk setup time, t asu full iv 2 ns lrclk hold time, t ahld full iv 2 ns cec cec_clk frequency 3 full viii 3 12 100 mhz cec_clk accuracy full viii ?2 +2 % cec_clk duty cycle full viii 40 60 % i 2 c interface scl clock frequency full viii 400 4 khz sda setup time, t dsu full viii 100 ns sda hold time, t dho full viii 100 ns setup for start, t stasu full viii 0.6 s hold time for start, t stah full viii 0.6 s setup for stop, t stosu full viii 0.6 s bus free between stop and start, t buf full viii 1.3 s scl high, t high full viii 0.6 s scl low, t low full viii 1.3 s 1 see the section. explanation of test levels 2 12 mhz crystal for default register settings. 3 only applies to s/pdif if external mclk is used. 4 i 2 c data rates of 100 khz and 400 khz are supported.
adv7533 rev. 0 | page 6 of 12 the power supply noise sensitivity of the adv7533 is frequency dependent. therefore, the maximum noise limit for the pvdd is specified in mv rms vs. frequency (see figure 2 ). 70 60 50 40 30 20 10 0 1 10 100 1k 10k 09821-102 noise limit (mv rms) frequency (hz) figure 2. pvdd maximum noise limit mipi/dsi specifications unless noted, timing and levels comply with mipi dphy standards. table 2. dsi high speed (hs) specifications adv7533 parameters symbol temp test level min typ max unit dc specifications dsi input common mode voltage v cmrx 25c vii 70 330 mv dsi input high threshold v idth 25c vii 70 mv dsi input low threshold v idtl 25c vii ?70 mv dsi single-ended input high voltage v ihhs 25c vii 460 mv dsi single-ended input low voltage v ilhs 25c vii ?40 mv dsi single-ended threshold for termination enable v term-en 25c vii 450 mv differential input impedance z id 25c vii 80 100 125 ac specifications single channel data rate 25c iv 200 800 mbps data to clock setup time t setup 25c vii 0.15 ui inst data to clock hold time t hold 25c vii 0.15 ui inst dsi clock duty cycle 25c vii 45 50 55 % common-mode interference beyond 450 mhz ?v cmrx(hf) 25c vii 100 mv common-mode interference 50 mhz to 450 mhz ?v cmrx(lf) 25c vii ?50 +50 mv common-mode termination c cm 25c vii 60 pf
adv7533 rev. 0 | page 7 of 12 reference time clkp clkn 0.5ui inst + 1ui inst t setup t skew t clkp t hold 09821-002 figure 3. dsi data to clock timing definitions table 3. dsi low power specifications parameter symbol temp test level min typ max unit dc specifications logic 1 input voltage v ih 25c vii 880 mv logic 0 input voltage, not in ulp state v il 25c vii 550 mv input hysteresis v hyst 25c vii 25 mv ac specifications input pulse rejection e spike 25c vii 300 v ps minimum pulse width response t min-rx 25c vii 20 ns peak interference amplitude v int 25c vii 200 mv interference frequency f int 25c vii 450 mhz table 4. dsi pin specifications adv7533 parameter conditions temp test level min typ max unit dc specifications pin signal voltage range v pin 25c vii ?50 +1350 mv pin leakage current i leak 25c vii ?10 +10 a ground shift v gndsh 25c vii ?50 +50 mv transient pin voltage level v pin (absmax) 25c vii ?0.15 +1.45 v maximum transient time above v pin (max) or below v pin (min) t vpin (absmax) 25c vii 20 ns
adv7533 rev. 0 | page 8 of 12 absolute maximum ratings table 5. parameter rating digital inputs i 2 c (ddcsda, ddcscl, sda, scl) and hpd 5.5 v to ?0.3 v digital inputsmipi/dsi 1.8 v digital inputsvideo/audio inputs, cec_io, cec_clk 3.63 v to ?0.3 v digital output current 20 ma operating temperature range ?10c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution explanation of test levels i 100% production tested. ii 100% production tested at 25c and samp le tested at specified temperatures . iii sample tested only. iv parameter is guaranteed by desi gn and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing. vii limits defined by hdmi specification ; guaranteed by design and characterization testing. viii parameter is guaranteed by design.
adv7533 rev. 0 | page 9 of 12 pin configuration and fu nction descriptions adv7533 top view (ball side down) not to scale 09821-003 1 a b c d e f g 234 ball a1 corner 567 drxc? drx0? drx1? drx2? drx3? drxc+ drx0+ drx1+ drx2+ drx3+ v1p2 gnd v3p3 gnd gnd gnd gnd gnd gnd dvdd dvdd scl ddcsc l ddcsd a sclk/mclk sda v1p2 lrclk gnd gnd cecclk a2vdd cec spdif/i 2 s avdd dvdd pvdd pd hpd rext int tx2+ txc? txc+ tx0? tx0+ tx1? tx1+ tx2? figure 4. pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description f6, g6 drx3?/drx3+ i mipi/dsi differential pair for la ne 3. unused channel should be connected to ground. f5, g5 drx2?/drx2+ i mipi/dsi differential pair for la ne 2. unused channel should be connected to ground. f4, g4 drx1?/drx1+ i mipi/dsi differential pair for lane 1. f3, g3 drx0?/drx0+ i mipi/dsi differential pair for lane 0. f2, g2 drxc?/drxc+ i mipi/dsi differential clock. c3 pd i power-down. programmable polarity is determined at power-up. the i 2 c address and the pd polarity are set by the pd pin state when the supplies are applied to the adv7533. internally pulled up for 1; if 0 desired, pull down to ground with a 2 k resistor. supports typical cmos logic levels from 1.8 v up to 3.3 v. c5 r_ext i sets internal reference currents. place a 1 k resistor (1% tolerance) between this pin and ground. c4 hpd i hot plug detect signal. indicates to the interface whether the receiver is connected. 1.8 v to 5.0 v cmos logic level. c1 spdif/i2s i s/pdif or i 2 s audio data input. represents the s/pdif block or the two channels of audio available through i 2 s. supports typical cmos logic levels from1.8 v to 3.3 v. c2 sclk/mclk i audio clock. supports typical cmos logic leve ls from1.8 v to 3.3 v. unused input should be connected to ground. d3 lrclk i audio left/right clock input. supports typical cmos logic levels from1.8 v to 3.3 v. unused input should be connected to ground. b7, a7 txc?/txc+ o differential clock output. differenti al clock output at pixel clock rate; tmds logic level. a2, a1 tx2?/tx2+ o differential output channel 2. differential o utput of the red data at 10 the pixel clock rate; tmds logic level. a4, a3 tx1?/tx1+ o differential output channel 1. differential output of the green data at 10 the pixel clock rate; tmds logic level. a6, a5 tx0?/tx0+ o differential output channel 0. differential o utput of the blue data at 10 the pixel clock rate; tmds logic level. d5 int o interrupt. cmos logic level. a 2 k pull-up resistor to interrupt the microcontroller i/o supply is recommended. this is a low active signal. b4 avdd p 1.8 v power supply for tmds outputs. should be filtered and as quiet as possible. d4, e3 v1p2 p digital logic supply (1.2 v or 1.8 v). set to 1.2 v for lowest power consumption. should be filtered and as quiet as possible.
adv7533 rev. 0 | page 10 of 12 pin no. mnemonic type 1 description g7 a2vdd p 1.8 v power supply for mipi/dphy input. should be filtered and as quiet as possible. e2, e4, g1 dvdd p 1.8 v power supply for digital and i/o power supply. supply power to the digital logic and i/os. should be filtered and as quiet as possible. c6 pvdd p 1.8 v power supply for the pll. should be filter ed and as quiet as possible. this supply is the most noise sensitive. b1 v3p3 p 3.3 v programming pin for hdcp nonvolatile memory. b2, b3, b5, b6, c7, e1, e7, f1, f7 gnd p ground for all domains. e5 sda c serial port data i/o. serves as the serial por t data i/o slave for register access. supports cmos logic levels from 1.8 v to 3.3 v. e6 scl c serial port data clock. serv es as the serial port data clock slave for register access. supports cmos logic levels from 1.8 v to 3.3 v. d2 ddcsda c serial port data i/o to receiver. serves as the master to the ddc bus. 5 v cmos logic level. d1 ddcscl c serial port data clock to receiver. serves as the master clock for the ddc bus. 5 v cmos logic level. d6 cec i/o cec i/o. if unused, pin should be connected to ground. d7 cec_clk i cec external clock. can be from 3 mhz to 100 mhz. settings default to 12 mhz. if unused, pin should be connected to ground. 1 i = input, o = output, p = power supply, c = control.
adv7533 rev. 0 | page 11 of 12 applications information design resources analog devices, inc., offers the following design resources: ? evaluation kits ? reference design schematics ? hardware and software guides ? software driver reference code ? hdmi compliance pretest services other support documentation is available under the nondisclosure agreement (nda) from atv_videotx_apps@analog.com . other references include the following: eia/cea-861e, which describes audio and video infoframes as well as the e-edid structure for hdmi. it is available from the consumer electronics association (cea). the hdmi v.1.3, the defining document for hdmi version 1.3, and the hdmi compliance test specification version 1.3 are available from hdmi licensing, llc.
adv7533 rev. 0 | page 12 of 12 outline dimensions a b c d e f g 3.500 3.460 sq 3.420 1 234567 bottom view (ball side up) top view (ball side down) 3.000 ref sq 0.50 ref 0 8-17-2010-b ball a1 identifier 0.660 0.600 0.540 end view 0.270 0.240 0.210 0.390 0.360 0.330 0.360 0.320 0.280 coplanarity 0.05 seating plane figure 5. 49-ball wafer level chip scale package [wlcsp] 7 mm 7 mm body (cb-49-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adv7533bcbz-rl ?10c to +85c 49-ball wafer level chip scale package [wlcsp] cb-49-1 EVAL-ADV7533-SAZ evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high-definition mult imedia interface are trademarks or register ed trademarks of hdmi licensing llc in the united states and other countries. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09821-0-7/11(0)

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